1. Technical Field
The present invention relates to circuits and methods for signal transmission. The present invention pertains, more specifically, to improvements in the transmission of signal in a memory circuit or microprocessor which transmits in parallel a great number of signals in synchronisation with a predetermined clock signal, in a single semiconductor chip or between two semiconductor chips.
2. Technical Background
Conventionally, microprocessors that perform parallel signal processing or memory circuits, such as image memories, synchronous dynamic random access memories (SDRAMs), static random access memories (SRAMs), employ the following basic configuration for the drive of signal lines, in other words for the transmission of signals.
This basic configuration is illustrated with reference to FIG. 36. 100 and 101 are signal transmission lines each of which is formed by a single line. 102 and 103 are drivers, formed by inverters, for transmitting signals to the signal lines 100 and 101. 104 and 105 are receivers, formed by inverters, for receiving signals from the signal lines 100 and 101.
The operation of the configuration of FIG. 36 is illustrated by making reference to FIG. 37. For the case of the transmission of parallel signals in synchronization with a clock signal MCLK, an input signal Ain and an input signal Bin are taken in on the rising or falling edge of the clock signal MCLK (Ain and Bin are taken in on the rising edge in FIG. 37) and, at this timing, the drivers 102 and 103 are activated at the same time so as to drive the signal lines 100 and 101, whereby the input signals Ain and Bin are transmitted to the signal lines 100 and 101, respectively. On the other hand, the signals of the signal lines 100 and 101 are fed into the inputs of the receivers 104 and 105 on the rising or falling edge of the clock signal MCLK (the signals are fed to the inputs on the rising edge in FIG. 37) and, at this timing, the receivers 104 and 105 are activated at the same time so as to detect the signals of the signal lines, whereby a detection signal Aout and a detection signal Bout are provided from the receivers 104 and 105.
The conventional configuration, however, has some problems. For example, each of the signal transmission lines 100 and 101 is formed of a single line. As a result, signals of the signal line each indicate a potential difference between the post-variation potential of a signal line and the reference threshold voltage for signal identification of a corresponding receiver. For this reason, when taking into account power supply noise, it becomes necessary to set a greater potential amplitude for each signal line. As a result, greater electric power is consumed when transmitting signals. Additionally, there are effects of wiring delay determined by a multiplication product of the wiring capacitance and the wiring resistance of each signal line. The conventional configuration, therefore, suffers from the problem that a large amount of power is consumed, even in low-speed operations.
To cope with such a problem accompanied with the conventional configuration, a configuration is proposed in which signal lines other than the signal lines 100 and 101 are provided in the same number as each signal line 100 and 101 and, at the time of the transmission of signals through each signal line, the signals are differential-transmitted using a signal line and its corresponding signal line.
The potential amplitude of signal lines can be reduced by means of the foregoing configuration, which makes it possible to achieve power saving. In spite of such an advantage, the number of signal lines increases. If the number of parallel bits increases from 64 up to 128 in image memories or the like, this increases both the chip area and the product cost. For this reason, it is difficult for such a configuration to achieve small and low-cost circuits.